In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new NetBurst microarchitecture, "Foster", was slightly different from the desktop Pentium 4 ("Willamette"). It was a decent chip for workstations, but for server applications it was almost always outperformed by the older Cascades cores with a 2 MB L2 cache and AMD's Athlon MP. Combined with the need to use expensive Rambus Dynamic RAM, the Foster's sales were somewhat unimpressive.
At most two Foster processors could be accommodated in a symmetric multiprocessing (SMP) system built with a mainstream chipset, so a second version (Foster MP) was introduced with a 1 MB L3 cache and the Jackson Hyper-Threading capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions. The Foster shared the 80528 product code with Willamette.
PrestoniaIn 2002 Intel released a 130 nm version of Xeon branded CPU, codenamed "Prestonia". It supported Intel's new Hyper-Threading technology and had a 512 kB L2 cache. This was based on the "Northwood" Pentium 4 core. A new server chipset, E7500 (which allowed the use of dual-channel DDR SDRAM), was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by new chipsets: the E7501 for servers and the E7505 for workstations). The Prestonia performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.
"Gallatin" Gallatin Produced From March 2003 to 2004 Max. CPU clock rate 1500 MHz to 3200 MHz FSB speeds 400 MT/s to 533 MT/s Min. feature size 130 nm Instruction set x86 Microarchitecture NetBurst CPUID code 0F7x Product code 80537 Cores 1 L1 cache 8 kB + 12 kuOps trace cache L2 cache 512 kB L3 cache 1 MB, 2 MB, 4 MB Application DP and MP Server Package(s) Socket 603 Socket 604 Brand name(s) XeonSubsequent to the Prestonia was the "Gallatin", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version also performed much better than the Foster MP, and was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP branded Gallatin with 4 MB cache. The Xeon branded Prestonia and Gallatin were designated 80532, like Northwood.
Xeon (DP) & Xeon MP (64-bit) Nocona and Irwindale Main article: Pentium 4#PrescottDue to a lack of success with Intel's Itanium and Itanium 2 processors, AMD was able to introduce x86-64, a 64-bit extension to the x86 architecture. Intel followed suit by including Intel 64 (formerly EM64T; it is almost identical to AMD64) in the 90 nm version of the Pentium 4 ("Prescott"), and a Xeon version codenamed "Nocona" with 1 MB L2 cache was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for PCI Express, DDR-II and Serial ATA. The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play.
A slightly updated core called "Irwindale" was released in early 2005, with 2 MB L2 cache and the ability to have its clock speed reduced during low processor demand. Although it was a bit more competitive than the Nocona had been, independent tests showed that AMD's Opteron still outperformed Irwindale. Both of these Prescott-derived Xeons have the product code 80546.
Cranford and Potomac Main article: Pentium 4#Prescott64-bit Xeon MPs were introduced in April 2005. The cheaper "Cranford" was an MP version of Nocona, while the more expensive "Potomac" was a Cranford with 8 MB of L3 cache. Like Nocona and Irwindale, they also have product code 80546.
Dual-Core Xeon "Paxville DP" Paxville Produced From October 2005 to August 2008 Max. CPU clock rate 2667 MHz to 3000 MHz FSB speeds 667 MT/s to 800 MT/s Min. feature size 90 nm Instruction set x86 Microarchitecture NetBurst CPUID code 0F48 Product code 80551, 80560 Cores 2 L2 cache 2×2 MB Application DP Server, MP Server Package(s) LGA 771, Socket 604 Brand name(s) XeonThe first dual-core CPU branded Xeon, codenamed Paxville DP, product code 80551, was released by Intel on 10 October 2005. Paxville DP had NetBurst microarchitecture, and was a dual-core equivalent of the single-core Irwindale (related to the Pentium D branded "Smithfield"") with 4 MB of L2 Cache (2 MB per core). The only Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a 90 nm process.
7000-series "Paxville MP"An MP-capable version of Paxville DP, codenamed Paxville MP, product code 80560, was released on 1 November 2005. There are two versions: one with 2 MB of L2 Cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2.67 GHz and 3.0 GHz (model numbers 7020–7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.
Model Speed (GHz) L2 Cache (MB) FSB (MHz) TDP (W) 7020 2.66 2 × 1 667 165 7030 2.80 2 × 1 800 165 7040 3.00 2 × 2 667 165 7041 3.00 2 × 2 800 165 7100-series "Tulsa" Tulsa Produced From August 2006 to August 2008 Max. CPU clock rate 2500 MHz to 3500 MHz FSB speeds 667 MT/s to 800 MT/s Min. feature size 65 nm Instruction set x86 Microarchitecture NetBurst CPUID code 0F68 Product code 80550 Cores 2 L2 cache 2×1 MB L3 cache 16 MB Application MP Server Package(s) Socket 604 Brand name(s) Xeon 71xxReleased on 29 August 2006, the 7100 series, codenamed Tulsa (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MB of L2 cache (1 MB per core) and up to 16 MB of L3 cache. It uses Socket 604 . Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 GHz to 3.5 GHz (model numbers 7110N-7150N), and the M-line ranges from 2.6 GHz to 3.4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MB to 16 MB across the models.
Model Speed (GHz) L2 Cache (MB) L3 Cache (MB) FSB (MHz) TDP (W) 7110N 2.50 2 4 667 95 7110M 2.60 2 4 800 95 7120N 3.00 2 4 667 95 7120M 3.00 2 4 800 95 7130N 3.16 2 8 667 150 7130M 3.20 2 8 800 150 7140N 3.33 2 16 667 150 7140M 3.40 2 16 800 150 7150N 3.50 2 16 667 150 5000-series "Dempsey" Dempsey Produced From May 2006 to August 2008 Max. CPU clock rate 2500 MHz to 3730 MHz FSB speeds 667 MT/s to 1066 MT/s Min. feature size 65nm Instruction set x86 Microarchitecture NetBurst Cores 2 L2 cache 4 MB Application DP Server Package(s) LGA 771 Brand name(s) Xeon 50xxOn 23 May 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed Dempsey (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is a NetBurst microarchitecture processor produced using a 65 nm process, and is virtually identical to Intel's "Presler" Pentium Extreme Edition, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.50 GHz and 3.73 GHz (model numbers 5020–5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MB of L2 Cache (2 MB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: LGA 771, also known as Socket J. Dempsey was the first Xeon core in a long time to be somewhat competitive with its Opteron-based counterparts, although it could not claim a decisive lead in any performance metric – that would have to wait for its successor, the Woodcrest.
Model Speed (GHz) L2 Cache (MB) FSB (MHz) TDP (W) 5020 2.50 2 × 2 667 95 5030 2.66 2 × 2 667 95 5040 2.83 2 × 2 667 95 5050 3.00 2 × 2 667 95 5060 3.20 2 × 2 1066 130 5063 3.20 2 × 2 1066 95 5070 3.46 2 × 2 1066 130 5080 3.73 2 × 2 1066 130
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